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- This dual bidirectional I2C buffer is operational at 2.3V to 3.6V Vcc.
- The PCA9515A is a BiCMOS integrated circuit intended for I2C bus and SMBus systems applications.
- The device contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to be extended without degradation of system performance.
- The PCA9515A buffers both the serial data (SDA) and serial clock (SCL) signals on the I4C bus,
- while retaining all the operating modes and features of the I2C system.
- This enables two buses of 400-pF bus capacitance to be connected in an I2C application.
- The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length.
- Using the PCA9515A enables the system designer to isolate two halves of a bus, accommodating more I2C devices or longer trace lengths.
- The PCA9515A has an active-high enable (EN) input with an internal pullup, which allows the user to select when the repeater is active.
- This can be used to isolate a badly behaved slave on power-up reset.
- It never should change state during an IC operation, because disabling during a bus operation hangs the bus, and enabling part way through a bus cycle could confuse the I2C parts being enabled.
- The EN input should change state only when the global bus and the repeater port are in an idle state, to prevent system failures.
- The PCA9515A also can be used to run two buses: one at 5V interface levels and the other at 3.3V interface levels, or one at 400kHz operating frequency and the other at 100kHz operating frequency.
- If the two buses are operating at different frequencies, the 100kHz bus must be isolated when the 400kHz operation of the other bus is required.
- If the master is running at 400kHz， the maximum system operating frequency may be less than 400 kHz, because of the delays that are added by the repeater.
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